Lead Design Engineer

About This Role

• Lead cutting-edge electrical and functional validation for next-generation DDR interfaces such as DDR5, LPDDR5, LPDDR6, HBM4 and GDDR7.
• Design and execute innovative testing strategies to accelerate post-silicon bring-up.
• Transform raw data into actionable insights through advanced analysis and visualization.
• Resolve complex issues by driving JIRA-based debug workflows and collaborating across teams.
• Deliver high-impact characterization reports that influence product decisions and customer success.
• Automate using Python for validation, data processing, and reporting.
• Be the go-to expert for customer DDR IP challenges, ensuring rapid debug and world-class technical support.
• Tech + 4 years’ experience or B.
• Tech with 6 years’ experience.
• The annual salary range for California is $114,800 to $213,200.
• You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
• Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
• Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
• Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
• We’re doing work that matters.
• Help us solve what others can’t.