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What You'll Do
- Methodology Strategy: Define and own the long-term DV architecture, focusing on scalability across multiple processor variants and generations.
- Verification Infrastructure: Architect simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
- Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis.
- Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.
- Mentorship: Provide technical direction and set the standard for quality and metric-driven verification (MDV) across global teams.
- Required Qualifications: B.Tech/M.Tech in ECE with 4 to 8 years of experience in SoC/CPU/DSP verification.
- Deep expertise in SystemVerilog/UVM and C/C++ for architectural modeling.
- Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
- Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
- Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.
- We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
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141 positions
Job ID
/job/PUNE-04/Lead-Design-Engineer_R54254-1
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