Opens cadence.wd1.myworkdayjobs.com in a new tab
What You'll Do
- s: Taking ownership and quickly drive to resolution product issues reported by field AEs and customers.
- Debug customer reported failures, produce test cases to replicate failure and log issues with HSV R&D teams.
- Recommend potential workaround or application level solutions to customers when necessary.
- Test R&D fixes/patches.
- Work with customer and internal groups to spec out enhancement requests.
- Testing new product features for future s/w releases or h/w platform, including participation in internal beta activities.
- Position Requirements: Requires a BS-EE/CE (MS-EE/CE preferred) with a minimum of 5 years experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.
- Strong knowledge of design debug techniques and a strong understanding in logic design.
- Knowledgeable in verification methodologies for complex EDA environments.
- Proficiency in HDL language like Verilog, SystemVerilog and VHDL.
- Ability to create test cases to replicate customer issues quickly.
- Proficiency in Unix/Linux scripting languages (ksh/bash/csh).
- Proficiency in PCIe, USB and Ethernet protocol.
- Proficiency in TBA, SVA, SV coverage, Low Power(UPF).
- UVM experience is a plus.
- Experience with emulation, Cadence's Palladium product preferred.
- Excellent communication skills.
- Must have ability to communicate complex issue to internal teams and customers in a clear and concise manner.
- Occasional travel may be required to resolve critical customer issues. undefined We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
Your application goes straight to Cadence Design Systems.
More from Cadence Design Systems (614 roles)
Cadence Design Systems
Ontologies & Knowledge Graphs (Agentic AI, Surrogates, Physical AI)
PUNE 05|Other
Cadence Design Systems
Ontologies & Knowledge Graphs (Agentic AI, Surrogates, Physical AI)
PUNE 05|Other
Cadence Design Systems
Software Engineer II: R&D Hardware Verification
BELO HORIZONTE|Verification
Opens cadence.wd1.myworkdayjobs.com in a new tab
Specialisation
Open roles at Cadence Design Systems
614 positions
Job ID
/job/SHANGHAI/Lead-Customer-Engagement-Engineer_R56543
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — freeSimilar Other roles
Samsung Semiconductor
Staff Engineer, ML Profiling Tools
San Jose, California, United States|Other
Samsung Semiconductor
Senior Staff Engineer, Thermal Simulation
San Jose, California, United States|Other
Samsung Semiconductor
Senior Engineer, SSD Qualification
San Jose, California, United States|Other
Samsung Semiconductor
Principal Engineer, Architecture & Performance Research for Data Center and Agentic AI CPU
San Jose, California, United States|Other