Lead Application Engineer

Overview

• At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
• Principal Application Engineer (Front-end Verification) Position Description: 1.
• Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
• Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
• Train, ramp-up and accompany customer project.
• Conduct basic and advanced trainings, presentations and demos as necessary.
• Providing technical expertise to address clients’ queries, which need expert involvement.
• Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.
• Position Requirements: Over 2~8 years’ experience in the following areas: 1.
• Design experience in Verilog/VHDL for IP or SoC chip level.
• HW verification with knowledge of SystemVerilog/VHDL and HDL simulators 3.
• FPGA prototyping project experience 4.
• Experience with hardware emulator or accelerator is a big advantage 5.
• Advanced Verification Methodology like UVM is a plus 6.
• Knowledge of Unix and Linux is highly desired 7.
• Strong verbal and written communication skills in English 8.
• Strong teamwork skills with good human relationship We’re doing work that matters.
• Help us solve what others can’t.