Lead Application Engineer

Overview

• At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
• This position requires solid understanding of IC design technology and foundry process/methodology in analog layouts.
• It is essential to have a very good understanding of analog layout design fundamentals, advance node virtuoso techfile constraints and in-depth knowledge and hands-on experience on writing skill scripts to perform various layout automation tasks.
• The candidate should have knowledge of complete analog back-end flow from top level floorplanning down to complex block level layouts, physical verification, extraction, EMIR analysis etc., with proficiency in Cadence layout tools specifically Virtuoso with advance node exposure.
• Prior Design experience using Cadence Custom IC Physical Design tools (Virtuoso) and flows including chip integration and signoff is an added advantage.
• Exposure to AI/ML assisted tools and EDA workflow automation to improve designer’s efficiency and layout productivity, is a big plus.
• or equivalent with 5 to 10 years of relevant experience We’re doing work that matters.
• Help us solve what others can’t.