Lead Analog Layout Design Engineer

What You'll Do

• Design of High Speed SERDES for UCIe products at data rates up to 64 Gbps on leading edge technology nodes (e.g. 2nm FinFET CMOS) Design quality layouts of analog/mixed-signal circuit blocks, working in collaboration with circuit designers Responsibilities include all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules Participate in technical leadership of the team in the areas of layout design from block level to PHY top level integration and sign off Work with global teams (US, west coast and east coast), which work in different time-zones Job Qualifications: Candidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development Proficient layout design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency Working with custom layout designers from groups all over the world to build high quality IP and test chips Working with circuit designers and project managers from groups all over the world to understand their technical and schedule needs Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment BEng, MEng or PhD Additional Skills/Preferences: Cadence tool experience and design experience at >10Gbps and in 10% We’re doing work that matters.
• Help us solve what others can’t.