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Overview

  • At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
  • To provide key technical support in digital IC design implementation.
  • To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power designs.
  • Have real design experience including logic equivalence checking, logic synthesis, 4.Have rich experience for RTL debug, RTL timing and power analysis.
  • 5: Rich experience for Synthesis flow, and be familiar with backend implementation Position Requirements: 1.Master/Bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications.
  • Eager to learn new technologies, and willing to promote new technologies to customers 3.Requires working knowledge of one or more programming languages, and effective communication and soft skills.
  • Ability to debug all kinds of logic equivalent checking issues with formal tools(LEC, etc).
  • Ability to understand the low power design with UPF, IEEE1801, CPF,etc.
  • Have knowledge or experience in debugging the low power design issue with static check tools(ie.
  • Have experience in STA flow.
  • Have knowledge or experience in RTL coding is Plus.
  • We’re doing work that matters.
  • Help us solve what others can’t.

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/job/SHANGHAI/Frontend-Engineer_R52457

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