Digital Electronics Principal Verification Engineer

What You'll Do

• Development of Verification and Emulation Environments for complex Chiplet Designs Development of UVM-SV Scoreboards for self-checking regressions Development of Functional Coverage as part of Metric Driven Verification Environments Development of SystemVerilog Assertions for use in Formal and Simulation Environments Development of Emulation Environments based on Cadences Palladium Emulator Product Integration of Cadence Verification IP (VIP) for Simulation Environments Integration of Accelerated VIP (AVIP) for Emulation Environments Definition and Management of Verification Plans (vPlans) using Cadence vManager tools Creation and Management of Automated Regression Environments, e.g.
• Jenkins, GIT Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001 Close Collaboration with Architects and Design Engineers to debug complex test scenarios Job Qualifications: Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline 10+ years’ experience in microelectronics/EDA industry Experience of Verilog RTL Design essential Experience of Metric Driven Verification (MDV) essential Experience of Formal Verification Methodologies essential Excellent oral and written English essential Self-motivated with excellent planning, interpersonal, and communication skills Additional Skills/Preferences: Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
• We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
• We’re doing work that matters.
• Help us solve what others can’t.