Design Engineer II

What You'll Do

• EXp:2- 5 Years Physical design implementation of state-of-the-art Cadence IPs using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools.
• PPA characterization and optimization of these performance-oriented and power-oriented best-in-class IP cores for advanced process nodes, such as 7nm/5nm/3nm/2nm and beyond.
• Development, automation and maintenance of EDA flows and scripts for physical implementation.
• Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
• Participate in benchmarking PPAs for customer engagements.
• Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification.
• Experience with Cadence digital design tools will be an added advantage.
• Hands on scripting languages like Python, Perl, TCL, Unix shell, etc.
• Strong understanding of digital logic design, processor design, and computer architecture is desirable.
• Should have excellent communication, analytical and problem solving skills.
• Should be self-motivated and good team player.
• We’re doing work that matters.
• Help us solve what others can’t.