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What You'll Do
- Drive quality strategies and sign-off methodologies for Foundation IP.
- Lead QA reviews, audits, and compliance for IP deliverables (Ex : Review of DRC/LVS, timing, reliability).
- Analyze silicon and customer data to improve quality processes.
- Collaborate with design, validation, and customer teams.
- Mentor engineers and advocate for quality-first practices.
Qualifications
- B.S./M.S. in Electrical or Computer Engineering. 4+ years in semiconductor IP QA/design with strong foundation IP expertise.
- Proficiency with EDA tools (Cadence, Synopsys, Mentor).
- Knowledge of quality standards and silicon validation.
- Preferred: Background in advanced nodes, PDKs or memory validation.
- Experience in EDA view generation and validation.
- Why Cadence? Join an award-winning, collaborative culture working on cutting-edge technologies powering AI, 5G, automotive, and cloud computing.
- We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
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Specialisation
Open roles at Cadence Design Systems
637 positions
Job ID
/job/HYDERABAD/Design-Engineer-II_R54319
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