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What You'll Do

  • Contribute to the RTL design of blocks within high-speed Ethernet MAC, PCS, and FEC IP cores (10G through 1.6T), from micro-architecture through coding, lint, and CDC sign-off Work with the latest IEEE 802.3dj and Ultra Ethernet Consortium (UEC) specifications, contributing to architecture discussions on multi-rate, multi-port controller designs Collaborate closely with verification engineers on test plan reviews, coverage, and bring-up of new features Partner with back-end teams on synthesis, timing closure, and area/power trade-offs for configurable IP delivery Participate in design and code reviews, contributing to continuous improvement in design quality across the team Job Qualifications: Bachelor’s or Master’s degree in Electronic/Electrical Engineering, Computer Engineering, or a related discipline Experience in digital design through one or more of the following: Approximately 2+ years of industry experience in RTL design (ASIC or FPGA), or A research-based Master’s degree (MEng / MSc) in a relevant area such as digital design, networking, communications, or signal processing, or Equivalent hands-on experience demonstrating strong RTL design capability Working knowledge of Verilog or SystemVerilog, and core digital design fundamentals (e.g.
  • RTL design, FSMs, clocking, CDC, timing) Analytical and problem-solving skills, with the ability to take a design from specification through to implementation with support from the wider team Good communication skills and ability to collaborate effectively across design, verification, and back-end teams Additional Skills/Preferences: Experience with simulation and debug tools (e.g.
  • Xcelium, VCS, ModelSim, or similar) Exposure to Ethernet standards or high-speed networking Awareness of Forward Error Correction (FEC) or signal integrity concepts Check what we can offer you: Competitive salary 25 days holiday per year Private Medical and Dental plans, Income Protection and Life Insurance Group Personal Pension Plan Cycle to work scheme and gym subsidy 5 days paid time to volunteer to give back to our communities Employee Stock Purchase Plan The opportunity to work for a Great Place to Work© & Fortune 100 organization Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
  • We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
  • We’re doing work that matters.
  • Help us solve what others can’t.

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Open roles at Cadence Design Systems
646 positions
Job ID
/job/CORK-01/Design-Engineer-II_R55063

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