Design Enablement Engineer II

What You'll Do

• Leverage silicon verification platform and environment to create necessary post-silicon infrastructure, methodology and automation to allow tests executed in a timely and efficient manner.
• Integrate silicon, HW, firmware, and system software into a complete system which includes various InfiniBand and PCIe protocols, PXE booting, virtual machines, secure networks, Ethernet and Ethernet-over-InfiniBand, sockets and RPC calls, FPGA, microcontroller interfaces, JTAG, I2C, SPI, SERDES, memory and many other interfaces.
• Execute post-silicon tests to expose design issues, validate product against the specifications including performance, and qualify the design for production release.
• Review, replicate, and respond to customer issues.
• Perform initial analysis of error logs from customer design simulation runs.
• Debug and isolate system-level issues down to ASIC/FPGAs, host servers, subsystems, firmware modules, runtime diagnostics.
• Develop silicon and system stress tests.
• Leverage tests developed by other engineers.
• Package tests for production and field use.
• Define, develop and drive the implementation of validation automation environment Requirement Bachelor’s degree in Electrical Engineering or Computer Engineering.
• Master’s degree preferred.
• Must be proficient in one or more of the following disciplines – silicon simulation, silicon design, HW design, firmware design, silicon bring-up, system bring-up, HW/SW debug, verification and validation.
• Fluent in at least one functional scripting language, preferably but not limited to Python.
• Other languages are plus.
• Experience with embedded software/firmware, operating systems, and/or HW/SW interfaces is a plus Experience in developing, maintaining and operating automated engineering processes is a big plus.
• Strong interpersonal and communication skills, self-motivated and ability to work with cross-functions teams around the globe.
• We’re doing work that matters.
• Help us solve what others can’t.