Design Architect

About This Role

• We are seeking a skilled HW and/or Design Engineering Architect to lead build ing representative SoC sub-systems using partner systems (ARM, others) and Cadence design and verification collateral.
• The main task is to build ARM CSS based systems using Cadence AVIPS and IP, port these to Palladium/Protium hardware and software and ensure functional correctness and make recommendations for performance improvements.
• Experience with SoC design, verification , ARM bus protocols and performance analysis is required .
• Familiarity with or interest in developing new methodologies for SoC Integration and Verification Automation is a pl us.
• Skills needed : 1 5 -1 8 years of hands-on HW RTL development and verification experience Emulation experience on Palladium/Protium Expertise in AMBA and CHI protocols Knowledge with design/integration of SoC systems Experience with performance analysis of complex hardware-software systems.
• Familiarity with standard communication protocols PCIe, CXL is a plus Good communication skills, excellent inter-personal skills, motivated individual Ability to analyze and propose solutions to complex problems.
• We’re doing work that matters.
• Help us solve what others can’t.