CMOS SerDes or High-speed I/O, Lead Analog IC Design Engineer

Nice to Have

• Working knowledge of common SerDes standards and their electrical requirements. • Experience with Cadence design tools and laboratory testing. • Design experience at data rates above 10 Gbps and in process technologies below 28 nm.
• The annual salary range for California is $119,000 to $221,000.
• You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
• Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
• Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
• Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
• We’re doing work that matters.
• Help us solve what others can’t.