Application Engineering Director - IC Design Verification

What You'll Do

• Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support In collaboration with R&D, provide in-depth technical assistance working closely with your team to help support advanced verification flows and AI/ML applications to secure design wins Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions Understand the competitive landscape and continuously work on differentiating Cadence’s solutions Minimum requirements: BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field - 15+ years experience in the semiconductor industry - Have a good understanding and working knowledge with SystemVerilog, Verilog and UVM testbench architecture - Strong verbal and written communication skills - Digital design experience and Knowledge of design fundamentals such as architecture & micro-architecture - Ability to interact effectively with both external customers and internally with the AE and R&D teams The annual salary range for California is $157,500 to $292,500.
• You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
• Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
• Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
• Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
• We’re doing work that matters.
• Help us solve what others can’t.