Application Engineer Manager – Formal Verification and Functional Simulation

What You'll Do

• Help customers enhance their verification productivity by debugging complex issues and providing innovative solutions using Formal Verification and Functional Simulation tools and flows.
• Actively support customers on Formal Verification (Jasper and related applications) and Functional Simulation (Xcelium-based flows), including hybrid formal + simulation methodologies.
• Work closely with R&D and Product Engineering to identify, prioritize, and drive product improvements based on customer usage, formal analysis, and simulation feedback.
• Establish strong technical credibility and rapport with customers, becoming the trusted technical advisor and go-to expert for formal and simulation verification topics.
• Assume a technical leadership role within the team, guiding verification strategies, methodologies, and best practices.
• Ensure high-quality customer support across evaluations, deployments, and production engagements.
• Drive the creation of high-impact technical content, including knowledge articles, tool adoption kits, best-practice documents, and verification methodology guidelines to increase customer self-service.
• Collaborate closely with worldwide AE teams, actively mentoring, coaching, and developing engineers, while promoting global knowledge sharing.
• Partner with Sales and TFO teams to define and execute account support and technical engagement strategies.
• Deliver out-of-the-box technical solutions to customer challenges using tool capabilities, methodology optimization, automation, and scripting.
• Deploy and promote ML- and AI-assisted verification solutions to improve productivity, coverage, and debug efficiency.
• Analyze complex customer problems, isolate root causes, and ensure high-quality CCRs are created for efficient R&D resolution.
• Minimum Requirements Complete Bachelor’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Strong experience with Verification methodologies, with deep expertise in one or more of the following areas: Formal Verification (e.g., Jasper, FPV, CDC, connectivity, low-power, or other formal apps) Functional Simulation (Xcelium, UVM-based flows, coverage, regressions) Solid understanding of assertion-based verification, coverage concepts, verification sign-off criteria, and debug methodologies.
• Experience integrating Formal Verification with Simulation flows to accelerate verification closure and improve coverage.
• Knowledge of scripting and flow automation (e.g., Tcl, Python, Perl, shell) is a strong plus.
• Proven debugging skills, with the ability to identify critical issues and prioritize effectively in complex verification environments.
• Experience leading or mentoring a small to mid-size team of engineers is a plus.
• Strong communication skills and experience working directly with customers in technically complex engagements.
• Additional Job Details: Employment category: CLT Employment term: 40 hours/week Work location: Belo Horizonte, Brazil Competitive benefits package About Cadence Design Systems Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain—from chip design to chip packaging, boards, and systems.
• We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play.
• Our solutions support markets such as mobile, consumer, cloud datacenter, automotive, aerospace, IoT, and industrial.
• For more information, visit: http://www.cadence.com We’re doing work that matters.
• Help us solve what others can’t.