Subsystem/SoC Level Verification Engineer

About This Role

• He/she should have strong knowledge of the following with 12-15 years of experience in Ethernet Subsystem/SoC Level Functional verification Working experience in Ethernet Subsystem/SoC verification Expertise to develop verification environments using SystemVerilog and UVM Expertise to develop BFMs / Checkers / monitors / Scoreboards Must have developed block/system level verification plans and tests.
• Must have capability to debug test failures to find the root cause.
• Must have worked on code / functional coverage.
• Experience in constrained random verification.
• We will also consider qualified applicants with arrest and conviction records consistent with local law.
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.