Sr. Verification Engineer

About This Role

• We are looking for highly skilled and efficient Design Verification engineers for the High Speed Serdes Team, a part of Physical Layer Products Group at Broadcom.
• What you will be doing • Responsible for planning, verification and coverage closures of RTL mainly dealing with Ethernet, SerDes interfaces, based on UVM methodology • Identification and creation of functional coverage and following the coverage driven methodology • Work closely with the design team and verification teams to close any assigned tasks • Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design • Collaborate with the post-silicon teams on a need to basis What we are looking for • B.E./B.Tech/M.Tech with 6+ years of relevant experience • Self-motivated person with strong Background in planning, developing and working in functional coverage based constrained random verification environments • Expertise in Block, sub-system and top level verification • Expertise in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug • Experience on integration and working with C-reference models in SV test benches • Experience in scripting like perl/python/shell • Experience in Gate level simulations with SDF annotation What will make you stand out • Knowledge of IEEE 802.3 Physical layer clauses like Cl.72, 93, 91 etc. is a plus • Very high speed SerDes IP verification experience is a nice to have • Excellent knowledge of PCIE protocol - Gen3 and above is a plus • Good understanding of the system level architecture of PCIE/CXL-based designs is a plus • Strong Interpersonal and communication skills • Experience of being part of a complete life cycle of the IP verification process System specification to signoff • Experience in verifying complex verification blocks like PLL calibrations, multi clock, reset domain designs and mixed signal interfaces is a big plus. • Deeper understanding of PLLs/CDR concepts/AMS interfaces and networking IP designs is a plus.
• We will also consider qualified applicants with arrest and conviction records consistent with local law.
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.