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About This Role
- Broadcom’s Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes.
- Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.
- Define the digital architecture and verification strategies for complex AMS and IO subsytems Design, synthesis, and verification of Verilog/SystemVerilog RTL.
- Analysis, debug, and resolution of Lint and CDC issues in the design.
- Design convergence to timing closure utilizing RTL optimization strategies.
- Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
- Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
- Drive comprehensive test plans to ensure quality of design.
- Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
- Create and maintain detailed specification, design, and verification documentation.
- Job Requirements MS +10 years of relevant industry experience.
- Experience with digital implementation flow from RTL synthesis to timing closure.
- Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
- Experience with Tessent tool for DFT insertion and verification Proficient with Perl, Python and Tcl scripting.
- Strong problem solving skills with attention to detail.
- Must be self-motivated and able to work effectively across internal and external engineering teams.
- Highly Desired Qualifications Solid understanding of transistor-level circuit behavior.
- Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
- Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.
- Additional Job Description: Compensation and Benefits The annual base salary range for this position is $127,100 - $203,400.
- This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
- Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
- The company follows all applicable laws for Paid Family Leave and other leaves of absence.
- We will also consider qualified applicants with arrest and conviction records consistent with local law.
- If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Salary range
₹5-12 LPA to ₹40-70 LPA
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398 positions
Job ID
/job/USA-AZ-Chandler-North-Juniper-Drive/RTL-Design-Engineer_R025142-1
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