Principal Physical Design Engineer

About This Role

• Principal Physical Design Engineer — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — Physical Design Team in APD Broadcom’s ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions.
• We partner with the world’s most innovative technology companies—spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders—to co-design and manufacture complex, custom ASICs that power the modern digital backbone.
• The Physical Design team within APD is the world-class execution engine behind the industry's most advanced custom silicon.
• We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges.We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success.
• What Defines Our Physical Design Team Pioneering First-Pass Silicon in 3nm/2nm: Our team consistently pushes the boundary of physics, taking the largest and most complex die sizes from floorplan to tapeout on leading-edge foundry nodes (N7, N5, N3, and N2).
• Record-Breaking Scale & Complexity: We regularly execute full-chip physical implementation for ultra-large-scale ASICs exceeding tens of billions of transistors, multi-gigahertz clock frequencies, and dense multi-die 2.5D/3D integration (CoWoS, HBM3/4, chiplet architectures).
• Methodology & Flow Leadership: We develop and maintain cutting-edge in-house (AI Driven) automation and methodology across different EDA tools, setting the benchmark for signoff quality and turn-around-time (TAT).
• About the Role Broadcom’s ASIC Products Division (APD) is looking for a Principal Physical Design Engineer to lead physical design implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs.
• In this role, you will drive complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14).
• Key Responsibilities Full-Flow Implementation: Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus Advanced Node Execution: Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced technology nodes (5nm, 3nm, 2nm) using multi-patterning and complex metal stacks.
• Timing & Power Closure: Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization (static/dynamic IR-drop, EM) for signoff using PrimeTime, Voltus, or RedHawk.
• Qualifications & Requirements Education: B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience: 12+ years of hands-on physical design experience successfully taping out complex high-frequency, ultra-large-scale networking or AI ASICs.
• Deep Sub-Micron Expertise: Direct experience executing tapeouts in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
• EDA Tool Mastery: High proficiency in major physical design tool flows: P&R: Cadence Innovus Timing/STA: Synopsys PrimeTime or Cadence Tempus Extraction & IR/EM: StarRC / QRC, RedHawk DRC/LVS: Siemens Calibre Automation Skills: Advanced TCL, Python, and Unix shell scripting for flow automation and database manipulation.
• Communication: Excellent technical leadership, problem-solving, and cross-functional communication skills.
• Preferred Qualifications Strong background in high-speed clock network implementation (H-tree, mesh, low-power CTS).
• Experience with power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating).
• Compensation and Benefits The annual base salary range for this position is USD 143,800.00 To USD 230,000.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
• All subject to relevant plan documents and award agreements.
• Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.
• We will also consider qualified applicants with arrest and conviction records consistent with local law.
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.