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About This Role
- As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.
- Key Responsibilities : Work closely with the ATE engineer on yield improvement and analysis.
- Develop ATE patterns, manage the hand-off process, and perform silicon debugging.
- Participate in block and chip-level DFT implementation, developing and executing all related tasks.
- Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.
- Perform ATPG and pattern simulation for both MBIST and scan.
- Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.
- Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology.
- Required Qualifications: BSEE with 8+ years of relevant experience or MSEE with 6+ years of relevant experience.
- Required experience in silicon bring-up and yield improvement.
- Solid understanding of DFT techniques.
- Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.
- Experience in MBIST architecture and insertion.
- Experience in analyzing and debugging simulation failures.
- Solid understanding of digital logic fundamentals.
- Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.
- Proficiency with Perl or other scripting languages.
- Strong communication and interpersonal skills.
- Plus: Experience in STA constraint development in DFT modes Additional Job Description: Compensation and Benefits The annual base salary range for this position is $108,000 - $192,000.
- This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
- Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
- The company follows all applicable laws for Paid Family Leave and other leaves of absence.
- We will also consider qualified applicants with arrest and conviction records consistent with local law.
- If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Tools & Skills
EDA Tools
Languages
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Specialisation
Salary range
₹5-10 LPA to ₹35-58 LPA
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Job ID
/job/USA-TX-Austin---River-Place-B7/DFT-Engineer_R024805
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