ASIC Verification Engineer

About This Role

• Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features Develop verification environments using SystemVerilog and UVM Architect and develop scalable and re-usable test benches, using the framework of the verification methodology Develop BFMs / Checkers / monitors / Scoreboards Build pseudo-random tests to verify and get full Functional coverage Debug Regression failures in RTL and Gatelevel simulations, analyze Functional Coverage gaps and improve tests to cover the gaps Document verification strategy including Test plans, Testbench, Random tests, etc.
• We will also consider qualified applicants with arrest and conviction records consistent with local law.
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.