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About This Role
- We are looking for highly skilled and efficient Design Verification engineers that want to verify new designs that can evolve rapidly over the next several generations in a very dynamic market using industry proven constrained random methodologies with SystemVerilog and UVM.
- You can become a member of an extremely skilled and efficient group of engineers working on PCIe and other host interfaces.
- The technology is constantly evolving and this provides a chance to work on leading edge technology that is also used in other product lines.
- This is a rare opportunity to be part of a successful product line.
- All aspects of Design Verification will be involved, along with opportunities for technical leadership.
- Skills: Self motivated personality with a strong presence to do things right.
- Need to have a strong sense of teamwork and ability to work well with others.
- Constrained random verification methodologies with experience driving completion via coverage closure.
- Preferable to have skills with SV and UVM, well versed in OOP.
- Experience with PCIe and experience with using 3rd party BFM is a strong plus.
- Looking for candidates with a good understanding of datapath flows.
- Tools/Languages: SystemVerilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...) Experience: BSEE + 8+ years of related experience, or MSEE + 6+ years of experience Be part of developing our next generation product in a series of high throughput Ethernet products that deliver unprecedented performance at critically important power efficiency.
- Additional Job Description: Compensation and Benefits The annual base salary range for this position is $91,200 - $152,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
- Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
- The company follows all applicable laws for Paid Family Leave and other leaves of absence.
- We will also consider qualified applicants with arrest and conviction records consistent with local law.
- If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Salary range
₹5-12 LPA to ₹40-70 LPA
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398 positions
Job ID
/job/USA-CA-Irvine-Alton-Parkway-Bldg-2/ASIC-Design-Verification-Engineer_R025189
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