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About This Role
- Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language.
- Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification.
- Understand Verilog-AMS modeling language Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) Familiar with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample-and-hold (S/H), comparators, DAC voltage converter, buffering and amplification, etc.
- Understand good coding of RTL of digital design (eg clock divider, decoder, FSM, etc) and testbench creation.
- Fully familiar with how to run SV .vs. schematic verification for a given leaf SV model.
- Familiar with Cadence linting & simulation tools (ncsim, xrun, vcs) and analog schematic editor.
- Hands-on skills in scripting languages (TCL/Perl/Python) Experience with using AI tools such as Cursor, chipAgents to generate analog SV models and testbench based on a given design spec.
- Experience : Bachelor's and 8+ years of related experience Additional Job Description: Compensation and Benefits The annual base salary range for this position is $120,000 - $192,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
- Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
- The company follows all applicable laws for Paid Family Leave and other leaves of absence.
- We will also consider qualified applicants with arrest and conviction records consistent with local law.
- If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Salary range
₹4-10 LPA to ₹40-75 LPA
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Job ID
/job/USA-CA-Irvine-Alton-Parkway-Bldg-1/Analog-Mixed-Signal-Verilog-Modeling-Design-Engineer_R024672
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