Staff Physical Design Engineer

Nice to Have

• Background in FPGA/eFPGA architecture , routing fabrics, or programmable logic optimization is a Plus Experience with timing model generation , hierarchical design abstraction , and SoC IP integration .
• Exposure to flow development, CAD automation , or methodology ownership is a plus.
• For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
• Department of Commerce - Bureau of Industry and Security and/or the U.S.
• Department of State - Directorate of Defense Trade Controls.
• As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
• We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
• EEO is the Law: Notice of Applicant Rights Under the Law .
• Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days The expected wage range for a new hire into this position is $154,841 to $232,261.
• Actual wage offered may vary depending on work location , experience, education, training, external market data, internal pay equity, or other bona fide factors.
• This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
• This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time , and other benefits.