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What You'll Do
- Digital Architecture & RTL Design Define RTL architecture, module boundaries, interfaces, and control logic.
- Develop and debug synthesizable SystemVerilog/VHDL RTL that meets functional, timing, and power requirements.
- Architect and implement state machines, datapaths, arithmetic units, protocol engines, and digital control loops.
- Perform design checks (lint, CDC, reset‑domain crossing, DFT readiness) and support synthesis/STA closure.
- Integration & Cross Functional Collaboration Lead or contribute to system or chip-level architecture planning Support mixed-signal simulations, co-simulation flows, and integration testplans.
- Collaborate with DV engineers to ensure correct verification scope, coverage, and feature signoff.
- Lead or aid in the development of a verification strategy, verification plan, and test strategy.
- Support the development of a UVM based testbench and the overall verification effort Identify and implement constrained random and directed tests for verification Contribute and support the overall verification efforts Ownership & Technical Leadership Lead design reviews, documentation, and technical mentoring of junior digital designers (P1–P3).
- Evaluate, propose, and introduce improvements to digital design methodologies and flows.
Requirements
- BS/MS in ECE, EE, CpE, or related field. 5–10 years experience in digital RTL design and subsystem ownership.
- Strong SystemVerilog/Verilog coding and debugging skills.
- Experience with CDC, lint, DFT, synthesis, and timing analysis.
- Strong scripting ability (Python/Perl/TCL).
- Excellent communication and cross‑team collaboration skills.
- For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
- Department of Commerce - Bureau of Industry and Security and/or the U.S.
- Department of State - Directorate of Defense Trade Controls.
- As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
- We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
- Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
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Job ID
/job/Philippines-Bonifacio-Global-City/Staff-Engineer--Digital-Design-Engineering_R260537-1
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