Senior Design Verification Engineer
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What You'll Do
- , but not limited to: Plan, develop, document, and execute verification plans across multiple platforms, including simulation and emulation.
- Build and enhance SystemVerilog UVM-based simulation environments, infrastructure, and verification flows at block, subsystem, and full-chip levels.
- Develop, simulate, and debug both constrained-random and directed test cases aligned with verification plans.
- Define and implement functional coverage models, assertions, and metrics to measure verification progress and closure.
- Drive verification reviews, analyze coverage results, and implement actions to close gaps and ensure completeness.
- Evaluate and unify different verification methodologies while continuously improving productivity and efficiency.
- Collaborate with global verification teams to integrate internal and third-party IP/VIP into the verification environment.
- Partner with cross-functional teams (design, architecture, software, implementation) to ensure robust design quality and timely project execution.
- Job qualifications Master’s degree in Computer/Electrical engineering or related field with strong background in digital design and design verification Experience with object-oriented programming, SystemVerilog/UVM, Python, Perl Experience with Cadence, Synopsys, and/or Mentor tools for simulation Experience with System and Digital modeling languages (MATLAB or SystemC) Overall exposure to the design/verification tape-out cycle is desirable Prior experience working with multi-site teams and 3rd party VIP will be valuable #LI-CC1 For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
- Department of Commerce - Bureau of Industry and Security and/or the U.S.
- Department of State - Directorate of Defense Trade Controls.
- As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
- We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
- Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
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Job ID
/job/Spain-Valencia-Cortes-Valencianas/Senior-Design-Verification-Engineer_R255775-1
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