Principal Physical verification Engineer

What You'll Do

• Own full-chip and block-level physical verification signoff, including DRC, LVS, ERC, PERC and antenna/ESD checks for multiple complex SoCs. - Drive tape-out readiness: manage PV schedules, track violations, converge to zero/signoff-acceptable errors, and deliver clean GDS. - Develop, maintain, and optimize PV flows and scripts (e.g., Calibre, ICV) for performance, robustness, and ease of use. - Define and enhance PERC and reliability rule checks (ESD, EOS, EM-related constraints, point-to-point resistance, high current-density paths) in collaboration with reliability, I/O, and analog teams. - Own the floorplanning and power grid planning to minimize PV iterations and avoid late-stage violations. - Own debugging of complex DRC/LVS/PERC violations, including corner-case connectivity, device recognition, FinFET-specific rules - restrictive spacing, coloring, cut-mask and EUV/multi-patterning constraints - Partner with CAD teams to validate and qualify new technology nodes, rule decks, and fill/DFM flows before project adoption. - Mentor and guide junior and senior engineers on PV best practices, root-cause analysis methodologies, and signoff criteria. - Act as primary technical interface to foundry and EDA vendors for PV and reliability issues, waivers, and methodology improvements.
• Required Qualifications - Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field. - Typically 10–15+ years of experience in physical verification for complex ASIC/SoC designs, including several successful production tape-outs as signoff owner. - Proven experience owning DRC/LVS/PERC signoff for at least one 5 nm (or sub-7 nm) production tape-out in a FinFET process - Deep hands-on expertise with industry-standard PV tools (e.g., Siemens Calibre, Synopsys IC Validator) for DRC, LVS, ERC, PERC and ANT/ESD checks. - Hands-on experience with Cadence Virtuoso-PV tool integration ( Virtuoso layout to Caliber/ICV for DRC/LVS/PERC) - Strong experience with advanced process nodes (e.g., 5 nm and below) and associated design-rule and reliability challenges. - Proven track record in driving full-chip PV signoff in digital-on-top, mixed-signal, or multi-voltage SoCs, including hierarchical flows and IP integration. - Solid scripting skills in at least one of: Python, Perl, Tcl, or Unix shell, for automation and flow development. - Experience with PERC-based reliability flows for ESD, EOS, LUP and current-density-based checks, including setup, customization, and signoff criteria definition. - Familiarity with DFM/DFY checks, density/fill strategies, and pattern-matching-driven rule decks - Strong understanding of physical design (place & route, timing closure, power integrity) and its interaction with PV signoff. - Excellent problem-solving, debug, and communication skills, with demonstrated ability to lead cross-functional technical closure.
• For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
• Department of Commerce - Bureau of Industry and Security and/or the U.S.
• Department of State - Directorate of Defense Trade Controls.
• As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
• We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
• Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days