Principal Engineer, Process Development Engineering

What You'll Do

• Design & Verification: Lead chip-level and IP-level ESD protection design, simulation, and verification (e.g., LVS, DRC, DFM).
• Engage in the development of protection devices and circuits to address Analog Devices’ IC product ESD robustness requirements.
• Ensure all products meet the target ESD release requirements or product-specific ESD robustness standards.
• Onboard in-house and external foundry process technologies with the objective of developing an ESD design eco-system consisting of ESD Intellectual Property and CAD verification tools.
• Characterization: Conduct electrical, ESD, and reliability testing of devices to create design rules.
• Methodology Development: Define ESD, EOS, and Latch-up (LUP) methodologies for silicon development.
• Develop and customize ESD layout/schematic verification tools, both in-house and industry-standard EDA tools.
• Collaboration: Act as a technical interface between design teams, foundries, and reliability teams on ESD performance.
• Apply lessons learned to improve ESD protection methods in new product designs.
• Document and publish best-practice ESD protection methodologies.
• Failure Analysis (FA): Conduct failure and root cause analysis when products do not meet ESD robustness acceptance levels and implement corrective actions to achieve the required levels.
• Mentorship: Mentor junior engineers on ESD principles and design techniques.
• Requirements Education: Typically requires a Bachelor's (10+ years), Master's (8+ years), or PhD (5+ years) in Electrical Engineering.
• Coursework and/or experience with integrated circuit design.
• Solid understanding of device physics.
• Background in ESD protection circuit design techniques.
• Experienced with circuit simulation and interconnect parasitic extraction from layout.
• Experience with device and circuit layout EDA tools such as Cadence, Virtuoso.
• Familiar with ESD verification tools such as PERC.
• Experience or knowledge of ESD simulation tools and techniques.
• Solid understanding of models used for ESD testing to include HBM, CDM and IEC-61000-4-2.
• Experienced with Transmission Line Pulse device/product measurement characterization techniques.
• Technical Skills: Deep knowledge of semiconductor physics, CMOS, FinFet, and ESD/EOS protection device design (e.g., SCR, diode, ggNMOS).
• Tools: Expertise in CAD tools like Cadence Virtuoso, and simulation tools like SPICE.
• Excellent verbal and written communication.
• Self-motivated, open to challenges, strong initiative, independent worker, team player, and respects For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
• Department of Commerce - Bureau of Industry and Security and/or the U.S.
• Department of State - Directorate of Defense Trade Controls.
• As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
• We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
• Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days