Principal Engineer, Design Verification Engineering
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Benefits
- (2 days/week work from home).
- Requirements : Must have a Master’s degree in Electrical Engineering, Computer Engineering or closely related technical discipline (willing to accept foreign education equivalent) and ten (10) years of experience as a Design Verification Engineer or related occupation performing pre-silicon design verification.
- Must also possess the following (quantitative experience requirements not applicable to this section): Demonstrated Expertise (“DE”) developing test benches using SystemVerilog and OVM or UVM including test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, and assertion-based verification techniques.
- DE in Verilog, C or C++, revision control systems such as Perforce or Git, EDA tools and scripting (Python, Perl or Shell) used to build infrastructure, tools, and flows for verification environments.
- DE architecting and implementing Design Verification infrastructure and executing the full verification cycle.
- DE with pre- and post-silicon verification test flow and automated test benches.
- DE with verification of ARM or RISC-V based sub-systems or SoCs.
- Contact: Eligible for employee referral program.
- Apply online at https://www.analog.com/en/careers.html and Reference Position Number: R263318 .
- For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
- Department of Commerce - Bureau of Industry and Security and/or the U.S.
- Department of State - Directorate of Defense Trade Controls.
- As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
- We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
- EEO is the Law: Notice of Applicant Rights Under the Law .
- Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days
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Salary range
₹5-12 LPA to ₹40-70 LPA
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Job ID
/job/US-TX-Austin-Plaza-on-the-Lake/Principal-Engineer--Design-Verification-Engineering_R263318
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