Principal Engineer, Design Verification

Requirements

• Bachelor's or Master's degree in Electrical or Computer Engineering - 10+ years of hands-on experience in SystemVerilog/UVM-based verification - 3+ years of technical leadership experience, including mentoring engineers, leading verification efforts on complex projects, or managing small teams - Demonstrated experience architecting verification environments for complex mixed-signal SoCs or power management ICs - Proven track record of defining and implementing DV strategies across multiple concurrent projects - Expert-level proficiency in EDA tools and automation (Python, TCL, Perl, Shell) for building verification infrastructure and flows - Experience with formal verification methodologies and tools (JasperGold, VC Formal, or equivalent) - Strong understanding of coverage-driven verification, including functional coverage modeling and closure strategies - Excellent communication skills with the ability to present technical content to diverse audiences, including executives Preferred Qualifications - Experience with portable stimulus standard (PSS) and graph-based verification approaches - Deep knowledge of analog/mixed-signal verification techniques including SV-RNM modeling - Experience with verification of ARM/RISC-V based sub-systems or complex SoCs - Expertise in power management IC verification, including multiphase DC-DC controllers, voltage regulators, and power sequencing - Experience with voltage interface protocols such as PMBUS, AVS, SVID, SVI3, I2C, SPI - Knowledge of emulation and FPGA prototyping methodologies for early software enablement - RTL design experience providing strong design-for-verification perspective - Experience building and scaling verification teams or capabilities - Track record of driving process improvements that measurably improved verification quality or efficiency - AI/ML tools for verification – keen interest and experience leveraging AI for coverage closure, test generation, debug, or productivity improvements - Proficiency with multiple verification platforms (Cadence, Synopsys, Mentor/Siemens) - Experience with continuous integration/continuous verification (CI/CV) pipelines - Familiarity with cloud-based verification and distributed simulation/regression management - Version control expertise (Git, Perforce) and collaborative development workflows - Verilog, C/C++, SystemC for modeling and verification - Strong analytical and debug skills with ability to drive complex issues to resolution For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
• Department of Commerce - Bureau of Industry and Security and/or the U.S.
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• As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
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• Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days