PD Director

What You'll Do

• Directed end-to-end RTL-to-GDSII execution across multiple SoC programs, driving synthesis, floorplanning, placement, CTS, routing, and signoff to achieve predictable tapeouts.
• Owned timing, power, and physical signoff strategy, including STA, SI, IR/EM analysis, ensuring first-pass silicon success and high design reliability.
• Drove PPA optimization at the architecture and implementation levels through congestion management, advanced routing methodologies, and library strategy.
• Established and enforced DRC/LVS closure methodologies, led physical verification, and streamlined ECO flows to meet aggressive tapeout schedules.
• Partnered with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals across the product lifecycle.
• Built and scaled high-performing physical design teams; mentored senior engineers and technical leads while fostering a culture of execution excellence.
• Defined and deployed automated design methodologies using TCL, Python, and Perl; collaborated with CAD teams to improve flow efficiency and scalability.
• Delivered multiple high-complexity designs on advanced nodes (22nm, 16nm, 5nm, 3nm), managing risk, schedules, and cross-functional dependencies.
• Championed low-power design strategies (UPF/CPF), enabling power-efficient architectures aligned with product requirements.
• Position Requirements Education : B.Tech/M.Tech (or higher) in Electrical/Electronics Engineering or related field.
• Experience: 15+ years in physical design with a proven track record of নেতৃত্ব and successful tapeouts of complex, high-performance SoCs across advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm and below).
• Technical Expertise: Deep expertise in full-chip physical design, including floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, and full signoff methodologies.
• Signoff & Quality : Strong command of STA, constraint development, and signoff closure (timing, SI, IR/EM), with a focus on first-pass silicon success and predictable delivery.
• Methodology & Innovation : Proven ability to define, drive, and scale design methodologies and flows to achieve QoR (PPA) targets, improve efficiency, and ensure execution predictability.
• Technology Depth : Solid understanding of device, interconnect, and circuit challenges in advanced/Udsm nodes, with experience navigating scaling complexities.
• Automation & CAD Collaboration: Proficiency in TCL, Python, or similar scripting, with a track record of driving automation and partnering with CAD teams for flow enhancements.
• Cross-functional Influence: Strong collaboration with RTL, DFT, packaging, product, and system teams to align on design, test, and manufacturing goals.
• Communication & Stakeholder Management : Excellent communication skills with the ability to influence executive stakeholders and operate effectively in global, cross-functional environments.
• For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
• Department of Commerce - Bureau of Industry and Security and/or the U.S.
• Department of State - Directorate of Defense Trade Controls.
• As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
• We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
• Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days