Digital Design Engineer, DFT

Requirements

• Masters of Science degree in Electrical Engineering, Computer Engineering or similar 2 years of directly related experience in ASIC/SoC DFT Good understanding of DFT architecture and planning Hands on scan insertion and ATPG Tool experience Hands on experience of DFT Compression Insertion, On-Chip Clock Control Insertion Hands on experience of Gate-level simulation with zero delay and SDF Good understanding of Failure Analysis Scripting: Perl/Python/Tcl Team-player: the ability to forge and maintain relationships with peer-organizations Strong written and verbal communication skills Preferred Qualifications Experience with Tessent DFT tools Good understanding of IEEE 1149 and JTAG Experience with LBIST and MBIST Experience with advanced DFT technologies like low power, SSN, Fault Grading.
• For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
• Department of Commerce - Bureau of Industry and Security and/or the U.S.
• Department of State - Directorate of Defense Trade Controls.
• As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
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• EEO is the Law: Notice of Applicant Rights Under the Law .
• Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days