Analog/Mixed-Signal Interview Questions: 30 Real Questions from India 2026

TL;DR. Analog and mixed-signal interviews in India in 2026 are a different beast from digital interviews. The questions are open-ended, the expected answers are physical and intuitive rather than algorithmic, and the bar at product companies is high because the talent pool is small. The 30 questions below are the ones I see most often when interviewing AMS candidates at Texas Instruments, Analog Devices, Qualcomm, NXP, and Broadcom. Almost every candidate stumbles on the same three: small-signal stability of feedback amplifiers, layout-induced offset and noise mechanisms, and the mathematics of switched-capacitor sampling.

I have been an analog designer at Texas Instruments for seven years and have run over 80 AMS interview panels. The strongest candidates do one thing the average ones do not — they translate a circuit on a whiteboard into a transistor-level intuition without picking up a calculator. That is what these 30 questions are designed to test.

How AMS interviews differ from digital interviews

If you are coming from an RTL or verification background and considering AMS, calibrate your expectations. Five differences shape the interview:

1. Whiteboard, not editor. Most AMS rounds happen on a whiteboard. You sketch a circuit, label the operating point, and reason about behaviour as elements change. Live coding is rare.
2. Physical reasoning. Questions assume you can move between a schematic, a Bode plot, and a layout in your head. "Why does this op-amp oscillate at 47C but not at 25C?" is a typical question.
3. Open-ended trade-offs. There are usually multiple right answers. The interviewer cares about which trade-offs you surface — area vs power, noise vs bandwidth, supply rejection vs PSRR.
4. Layout matters. AMS engineers must understand how layout affects circuit performance. Common-centroid, dummy devices, guard rings — these come up at every senior interview.
5. Math when it matters. You should know noise integration, GBW relationships, and small-signal analysis well enough to derive answers without a calculator.

The interview format at product companies

4-5 rounds is standard. A 3-5 year AMS engineer in India should expect:

1. Recruiter screen (15 min). Resume review, expected CTC, notice period.
2. Technical screen (45-60 min). Foundational analog questions — MOSFET regions, op-amp basics, op-amp topologies.
3. Onsite analog deep dive (60-90 min). Design a specific block (LDO, bandgap, op-amp, comparator) on the whiteboard. Walk through stability, noise, mismatch.
4. Onsite mixed-signal and layout (45-60 min). ADC, DAC, PLL, or layout questions depending on the role.
5. Hiring manager (30-45 min). Past project, silicon experience, debugging stories.

MOSFET and small-signal foundations (Q1-Q8)

Q1. Sketch the I-V curves of a MOSFET and explain the regions.

Three regions: cutoff (Vgs < Vt, no current), triode/linear (Vgs > Vt and Vds < Vgs - Vt, the device behaves like a voltage-controlled resistor), and saturation (Vgs > Vt and Vds > Vgs - Vt, the current is approximately constant with Vds and depends primarily on Vgs - Vt). Modern short-channel devices have significant channel-length modulation in saturation, so Id continues to rise slowly with Vds even past saturation onset.

Q2. What is gm and why does it matter?

gm (transconductance) is the small-signal change in drain current per change in gate-source voltage at a fixed Vds. It sets the gain of common-source amplifiers (gain ≈ -gm * Rload), the bandwidth of feedback loops, and the input-referred noise of analog blocks. For a long-channel device in saturation, gm = sqrt(2 * mu * Cox * (W/L) * Id). For a short-channel device biased near threshold, gm/Id approaches 1/(nVT), the limit of operation.

Q3. Explain output resistance ro.

ro is 1/(channel-length modulation slope) at the operating point. It sets the maximum gain achievable from a single-stage amplifier (intrinsic gain = gm * ro). Higher ro means higher gain but slower switching because the output node sees higher impedance. Cascoding multiplies ro by the gm-ro product of the cascode device, which is the standard trick for boosting gain.

Q4. What is the difference between strong inversion, moderate inversion, and weak inversion (subthreshold)?

Strong inversion: Vgs significantly above Vt. Drain current scales with (Vgs - Vt)^2. Moderate inversion: Vgs near Vt, ID transitioning between exponential and quadratic. Weak inversion: Vgs below Vt, drain current is exponentially small (similar to a BJT). Modern low-power AMS designs operate moderate to weak inversion to maximise gm/Id, trading bandwidth for power.

Q5. Derive the input-referred thermal noise of a common-source amplifier.

The drain current noise of a MOSFET is roughly 4kT * gamma * gm. Refer it back to the input by dividing by gm^2: input-referred noise voltage spectral density = 4kT * gamma / gm. Higher gm means lower noise — which is why noise budgets push gm up, even at the cost of power. Total integrated noise depends on bandwidth and the noise shape (1/f vs thermal).

Q6. What is 1/f (flicker) noise and why does it dominate at low frequencies?

1/f noise originates from charge trapping and detrapping in the MOSFET channel-oxide interface. It has a power spectral density that increases with decreasing frequency. PMOS devices typically have lower 1/f noise than NMOS because of buried-channel implants. For low-frequency AMS blocks (audio, sensor frontends), use larger device area (W*L) to reduce 1/f noise, since flicker noise is inversely proportional to area.

Q7. Sketch the small-signal model of a MOSFET in saturation.

Three components: a voltage-controlled current source (gm * Vgs), an output resistance ro between drain and source, and parasitic capacitances (Cgs, Cgd, Csb, Cdb, Cgb). For low-frequency hand analysis, drop the capacitors. For frequency response, include Cgs and Cgd at minimum.

Q8. What is the body effect and when does it matter?

When the source is not at the same potential as the bulk, the threshold voltage shifts. Vt becomes Vt0 + gamma * (sqrt(2*phi_F + Vsb) - sqrt(2*phi_F)). Critical for stacked devices in cascodes, source followers (Vt rises as Vsb rises, reducing gain), and any topology where source is not tied to the lowest rail. Modern triple-well processes let you tie body to source for analog signal-path devices to eliminate body effect.

Op-amp design and stability (Q9-Q15)

Q9. Sketch a two-stage Miller-compensated op-amp and explain each transistor's role.

First stage: differential pair (M1, M2) with current-source tail (M5) and current-mirror load (M3, M4). Second stage: common-source amplifier (M6) with current-source load (M7). Miller compensation: a capacitor Cc and (often) a nulling resistor Rz between the gate of M6 and the output. The diff pair sets input common mode and offset, the common-source second stage sets gain and slew, Cc sets the dominant pole at the output of stage 1.

Q10. Explain Miller compensation and why we add a nulling resistor.

Cc creates a low-frequency dominant pole by Miller-multiplying its capacitance at the output of the first stage. This guarantees stability in feedback. Side effect: a right-half-plane (RHP) zero at gm6/Cc that hurts phase margin. A nulling resistor Rz = 1/gm6 cancels the RHP zero by introducing a left-half-plane zero in the same place. Done correctly, the resulting op-amp has phase margin above 60 degrees and a clean step response.

Q11. What is gain-bandwidth product (GBW) and what determines it for a two-stage op-amp?

GBW = gm1 / (2*pi*Cc) for the standard two-stage Miller-compensated op-amp. The first-stage transconductance and the compensation capacitor set the unity-gain frequency. To increase GBW, increase gm1 (more current or wider devices) or decrease Cc (at the cost of phase margin and load capacitance tolerance).

Q12. Define phase margin. What's the minimum acceptable phase margin?

Phase margin is the difference between the loop's phase at unity gain and -180 degrees. Greater than 60 degrees is the conservative target — overshoot is below 5 percent and the step response is well-damped. 45 degrees is acceptable for some bandwidth-limited applications. Below 45 degrees, you see ringing and risk oscillation under PVT corners.

Q13. Design a folded cascode op-amp. What's the advantage over a two-stage?

Folded cascode is a single-stage topology: the diff pair feeds cascode devices that fold the signal current to a high-impedance node. Output is taken from that node. Advantages: high output swing limited only by Vds_sat overhead at top and bottom, single dominant pole (no Miller compensation needed), better PSRR than two-stage. Disadvantages: lower gain than two-stage Miller (intrinsic gain = gm1 * (ro || ro_cascode)), more current.

Q14. Why do we use rail-to-rail input op-amps?

For low-supply circuits (1.2V or below), the input common-mode range of a single-pair input stage is too restrictive. Rail-to-rail input uses two complementary diff pairs (NMOS and PMOS) operating in parallel, switching dominance based on input common mode. The catch: gm changes across the common-mode range, which complicates compensation and offset trim.

Q15. Walk through stability analysis using Bode plots.

Plot magnitude and phase of the loop gain (open-loop gain * feedback factor) on log frequency. The unity-gain frequency is where magnitude crosses 0 dB. Phase margin is 180 + phase(unity-gain). Look for poles (each adds -20 dB/decade and -90 degrees) and zeros (each adds +20 dB/decade and +90 degrees). The dominant pole sets bandwidth; non-dominant poles must be far enough above unity-gain to not erode phase margin.

Mixed-signal blocks (Q16-Q22)

Q16. What is the difference between a SAR ADC and a pipeline ADC?

SAR (Successive Approximation Register) does N comparisons sequentially per conversion to produce N bits. Throughput is one conversion per N+1 clock cycles. Power scales linearly with sample rate. Best for medium-resolution medium-speed conversions (10-14 bits, 1-100 MS/s). Pipeline does each bit in a separate stage and pipelines conversions through. Throughput is one conversion per clock cycle. Best for high-speed high-resolution (10-16 bits, 100 MS/s and up). SAR has lower latency, pipeline has higher throughput.

Q17. Design a 10-bit SAR ADC at 10 MS/s. Sketch the architecture.

Components: capacitive DAC (charge-redistribution), comparator, SAR control logic, sample-and-hold (often built into the DAC). Process: sample input onto the DAC array, then for each bit, switch the appropriate capacitor to compare DAC output to ground via the comparator, register the decision, repeat for N bits. Power-efficient because nothing static draws current except the comparator during decisions.

Q18. Explain bandgap reference. Why is it temperature-independent?

A bandgap reference combines two voltages with opposite temperature coefficients: VBE (PTAT-complementary, decreases with temperature, approximately -2 mV/C) and VT * ln(N) (PTAT, increases with temperature, approximately +0.085 mV/C per ratio). Adding them with the right scaling factor (typically VT * ln(N) * 22) cancels the temperature dependence around 1.25V. Modern designs use bipolar transistors, scaled diodes, or DTMOS structures depending on process.

Q19. Design a low-dropout regulator (LDO).

Standard topology: error amplifier compares output (divided by R1, R2) to bandgap reference. Error amplifier output drives a pass transistor (PMOS for low dropout). Output capacitor sets one pole, error amp output sets another. Stability is the hard part — the load and the cap form a pole that moves with load current. Solutions: type-2 compensation, internal compensation, or a deliberate ESR zero from the output cap.

Q20. What is PSRR and how do you improve it?

Power Supply Rejection Ratio measures how much supply ripple appears at the output relative to the supply. Improvements: use cascodes to isolate signal nodes from supply, design supply-independent biasing, add a clean reference for the bias current, and use differential signal paths so common-mode supply noise rejects.

Q21. What is settling time and why does it matter?

Settling time is how long an amplifier takes to reach within a specified error band of its final value after a step input. Critical for sample-and-holds, switched-capacitor circuits, and any sampled system. Linear settling depends on the amplifier's bandwidth; non-linear (slewing) settling depends on the slew rate (Islew/Cload). Total settling = slew time + linear settling time.

Q22. Explain charge injection in a sample-and-hold.

When a CMOS switch turns off, the channel charge it was holding must go somewhere. Half typically flows to each side. On the held capacitor side, this charge creates an offset proportional to switch size. Mitigations: dummy switches with reversed clock, bottom-plate sampling, complementary switches that cancel first-order injection, transmission-gate switches with matched NMOS/PMOS area.

Layout and silicon (Q23-Q30)

Q23. What is common-centroid layout and when do you use it?

Common-centroid layout places matched device pairs symmetrically around a common geometric centre. It cancels first-order linear gradients (process, temperature, mechanical stress) across the layout. Used for input differential pairs, current-mirror references, and any matching-critical pair. The unit cell is broken into multiple fingers and interleaved (e.g., A B B A or A B A B / B A B A patterns).

Q24. What are dummy devices and why do you add them?

Dummy devices are non-functional copies of a real device placed at the edges of an array to ensure the real devices on the edge see the same lithographic and etch environment as those in the middle. Without dummies, edge devices have systematically different characteristics than interior ones. Standard practice for matched pairs and arrays.

Q25. Explain offset in a differential pair and how to minimise it.

Offset is the input voltage required to zero the output current difference. Sources: Vt mismatch, beta (mu*Cox*W/L) mismatch, geometric asymmetry. Minimisation: maximise WL (offset proportional to 1/sqrt(WL)), use common-centroid layout, match operating points carefully, minimise gate-leakage at deep submicron. For high-precision applications, autozero or chopper stabilisation can reduce residual offset further.

Q26. What is chopper stabilisation?

Chopper stabilisation modulates an input signal up to a high frequency, amplifies it (where 1/f noise and offset are minimal), and demodulates back to baseband. The result: input-referred 1/f noise and offset reduce to thermal-noise levels. Trade-off: residual ripple at the chopping frequency, increased complexity, slightly higher noise from charge-injection mismatches.

Q27. Why does layout matter so much in analog design?

Three reasons. (1) Mismatch — small geometric or process variations between matched devices translate directly into offset and noise. (2) Parasitic coupling — substrate noise, supply IR drops, and capacitive coupling between signals all reach the circuit through layout, not schematic. (3) Reliability — current density, electromigration, and ESD all depend on metal width and layer choice. A schematic-correct AMS block with bad layout is a non-functional block.

Q28. Explain the difference between guard rings and substrate ties.

Substrate ties anchor the bulk to a known potential (typically ground for NMOS or VDD for PMOS in N-well) to prevent latch-up and reduce substrate noise. They are added everywhere. Guard rings are continuous P+ (around N-well) or N+ (around P-substrate) rings around sensitive devices that drain substrate current away from the protected device. Used around oscillators, sensitive analog inputs, and any block that must reject substrate noise.

Q29. Walk me through a real silicon failure you debugged.

Hiring managers want a story. Be specific. Example: "Our LDO oscillated at 105C but not at 25C across a sample of 30 dies. We bench-debugged with thermal stream and found the unity-gain frequency rose 30 percent at hot, pushing a non-dominant pole inside the unity-gain frequency. The fix: increase the compensation capacitor to push the dominant pole down further. We added 10 pF and the LDO was stable across all corners. Lesson: when designing for hot, simulate phase margin at the worst-case corner first, not at TT 25C."

Q30. What is your favourite analog block and why?

This question reveals depth. The right answer is not "op-amp" — that is too generic. Pick a block you have designed and can defend with conviction. "I love the bandgap because it sits at the intersection of physics, mathematics, and layout — every PVT corner challenges you to balance trade-offs." That kind of answer earns respect. Generic answers do not.

The 8-week prep plan

Week	Focus	Output
1-2	MOSFET fundamentals, small-signal models, biasing	Hand-derive Av, Rin, Rout for 5 single-stage topologies
3-4	Op-amp design — two-stage, folded cascode, telescopic	Sketch and stability-analyse 3 op-amp topologies on a whiteboard
5	Mixed-signal blocks — ADC, DAC, bandgap, LDO	Pick one block per day, sketch architecture, list trade-offs
6	Layout, matching, parasitics, mismatch	Review the layout of one block you've worked on, identify what drives mismatch
7	Past project deep-dive prep, mock interview	Write up 2 silicon-debug stories with full STAR structure
8	Review, sleep	Sleep, especially the night before

Where to go from here

If AMS is your target, read the AMS career guide for the career-progression view, including which subspecialties (RF, power, data conversion, sensor frontends) suit which backgrounds. For salary expectations, see the India 2026 salary guide. If you are deciding between AMS and digital, the RTL vs verification vs physical design comparison covers the digital paths.

Browse live AMS roles in India from Texas Instruments, Analog Devices, Qualcomm, NXP, Broadcom, and 25+ other chip companies — sourced directly from career pages.